1. Field of the Invention
The present invention relates to microelectronic devices, and in particular, to packaging for microelectronic devices.
2. Description of Related Art
FIG. 1 shows a prior art Integrated Circuit (IC) package 10, which includes a substrate or die carrier 12 with the IC die 14 mounted thereon. An underfill 16, used for mechanical support and electrical insulation, is interposed between the IC die 14 and the die carrier 12. An Integrated Heat Spreader (IHS) lid 18 is mounted to the die carrier 12 by way of a sealant 20. A Thermal Interface Material (TIM) 22 bonds the IC die 14 and the IHS lid 18 together for heat removal. Solder bumps are placed on bonding pads located both on the IC die 14 and the die carrier 12. In a “flip-chip” attachment process, the IC die 14 is flipped upside down and attached directly to the die carrier 12 by the solder bumps on the die 14 and the solder bumps on the carrier 12 joining to form the solder joints 24. These traditional flip chip packages, whether ball grid array (BGA) or pin grid array (PGA) packages, have solder bumps which are referred to as Control Collapsed Chip Connection (C4) bumps.
Many applications may benefit from thinned dice. However, large diameter wafers must be thicker in order to maintain structural integrity and planarity during a wide range of processing steps encountered during IC fabrication. As a practical matter, prior art bumped dice (such as the die 14) may only be thinned to a thickness of about 125 microns because of the presence of the solder bumps 24 to the IC die 14. More specifically, when a grind pad is used to thin the wafer by removing silicon from its backside, the front side of the wafer, which has the solder bumps, is mounted on a support substrate. As a consequence, the solder bumps may imprint on the thinned wafer. More specifically, where there is a bump, there is a force applied by the support substrate and where there is not a bump, a force is not applied by the support substrate. Hence, a special bump protection adhesive is required to fill in between the wafer and the support substrate to uniformly distribute the force. However, the support substrate and the adhesive needed to be removed after wafer thinning process is completed. The presence of the bumps generates great difficulty in removing the support and the adhesive, especially when the wafer is very thin (less than 50 microns thick). Likewise, it is not practical to thin the wafer prior to attaching the solder bumps. The typical wafer from which dice are produced has a thickness of about 775 microns. When the wafer's thickness is reduced to 125 microns or less, the wafer cannot support its own weight. Consequently, to fabricate the solder bumps to the thinned wafer, extra compensatory support for the thinned wafer is necessary, which would be expensive and complicated.
One issue which must be addressed in the connection of various different types of materials (i.e., die, die carrier, IHS, TIM, etc.) is the Coefficient of Thermal Expansion (CTE) for each material. The CTE is a measurement of the expansion and contraction of each material during heating and cooling cycles, respectively. A material having a higher CTE than the surrounding material it joins expands and contracts at a faster rate than the surrounding material when heated and cooled (e.g., after bonding), respectively, leading to a CTE mismatch which may cause stress and warpage. Local stress may be caused by a CTE mismatch between the solder bumps 24 (may be as tall as 15 to 50 microns) and a low k Interlayer Dielectric (ILD) layer. Global stress may be caused by a CTE mismatch between the IC die 14, IHS lid 18 and die carrier 12. In the prior art, the underfill 16 may be used to reduce global stress; however, it may be difficult to fill the relatively small gap between die 14 and die carrier 12 with the underfill 16. In the prior art, the local stress may be partially reduced by using “softer” solder material like SnPb in the solder balls, which may not be environmental friendly.
The thermal interface material (TIM) 22 in the prior art IC package 10 is a soft solder and has a thickness of around 200 microns. At this thickness, the TIM 22 may not deliver the thermal performance desired when the IC die 14 is a high performance processor die. If the thickness of the TIM 22 is made substantially less than this to achieve the desired thermal performance, it may be insufficient to bond together reliably the IC die 14 and IHS lid 18 because of the stress generated from CTE mismatch.
A dual Damascene process, which makes use of copper as an interconnect material, has been used in the prior art to form interconnection lines (traces) and vias between interconnected levels at the same time. The Dual Damascene process uses a metallization approach that fills trenches etched into an insulator, followed by a Chemical-Mechanical Polishing (CMP) step.